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19-0196; Rev 0; 10/93
NUAL KIT MA ATION HEET EVALU DATA S WS FOLLO
+5V, Low-Power, 12-Bit Serial ADCs
________________________________Features
o o o o o 12-Bit Resolution 12 LSB Integral Nonlinearity (MAX187A/MAX189A) Internal Track/Hold, 75kHz Sampling Rate Single +5V Operation Low Power: 2A Shutdown Current 1.5mA Operating Current o Internal 4.096V Buffered Reference (MAX187) o 3-Wire Serial Interface, Compatible with SPI, QSPI, and Microwire o Small-Footprint 8-Pin DIP and 16-Pin SO
__________________General Description
The MAX187/MAX189 serial 12-bit analog-to-digital converters (ADCs) operate from a single +5V supply and accept a 0V to 5V analog input. Both parts feature an 8.5s successive-approximation ADC, a fast track/hold (1.5s), an on-chip clock, and a high-speed 3-wire serial interface. The MAX187/MAX189 digitize signals at a 75ksps throughput rate. An external clock accesses data from the interface, which communicates without external hardware to most digital signal processors and microcontrollers. The interface is compatible with SPITM, QSPITM, and MicrowireTM. The MAX187 has an on-chip buffered reference, and the MAX189 requires an external reference. Both the MAX187 and MAX189 save space with 8-pin DIP and 16-pin SO packages. Power consumption is 7.5mW and reduces to only 10W in shutdown. Excellent AC characteristics and very low power consumption combined with ease of use and small package size make these converters ideal for remote DSP and sensor applications, or for circuits where power consumption and space are crucial.
MAX187/MAX189
_________________Ordering Information
PART MAX187ACPA MAX187BCPA MAX187CCPA MAX187ACWE MAX187BCWE MAX187CCWE MAX187BC/D TEMP. RANGE PIN-PACKAGE ERROR (LSB) 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 8 Plastic DIP 8 Plastic DIP 8 Plastic DIP 16 Wide SO 16 Wide SO 16 Wide SO Dice* 12 1 2 12 1 2 1
___________________________Applications
Portable Data Logging Remote Digital Signal Processing Isolated Data Acquisition High-Accuracy Process Control
Ordering Information continued on last page. * Dice are specified at TA = +25C, DC parameters only. ** Contact factory for availability and processing to MIL-STD-883.
________________Functional Diagram
OUTPUT SHIFT REGISTER 6 DOUT 8 SCLK
_________________Pin Configurations
TOP VIEW
GND
5 AV = 1.638 +2.5V BANDGAP REFERENCE (MAX187 ONLY) 10k (4.096V)
REFDAC REF+
V DD AIN 12-BIT SAR
1 2
8 7
SCLK CS DOUT GND
REF AIN
4 2
SHDN 3 REF 4
MAX187 MAX189
6 5
T/H COMPARATOR
MAX187 MAX189
VDD 1
7 BUFFER ENABLE/DISABLE CONTROL AND TIMING 3
DIP
CS SHDN
NOTE: PIN NUMBERS SHOWN ARE FOR 8-PIN DIPs ONLY.
Pin Configurations continued on last page.
TM SPI and QSPI are trademarks of Motorola. Microwire is a trademark of National Semiconductor.
________________________________________________________________ Maxim Integrated Products 1
Call toll free 1-800-998-8800 for free samples or literature.
+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V AIN to GND................................................-0.3V to (VDD + 0.3V) REF to GND ...............................................-0.3V to (VDD + 0.3V) Digital Inputs to GND.................................-0.3V to (VDD + 0.3V) Digital Outputs to GND..............................-0.3V to (VDD + 0.3V) SHDN to GND.............................................-0.3V to (VDD + 0.3V) REF Load Current (MAX187) .........................4.0mA Continuous REF Short-Circuit Duration (MAX187)................................20sec DOUT Current ..................................................................20mA Continuous Power Dissipation (TA = +70C) 8-Pin Plastic DIP (derate 9.09mW/C above +70C) ..500mW 16-Pin Wide SO (derate 8.70mW/C above +70C) ...478mW 8-Pin CERDIP (derate 8.00mW/C above +70C) ......440mW Operating Temperature Ranges: MAX187_C_ _/MAX189_C_ _.............................0C to +70C MAX187_E_ _/MAX189_E_ _ ..........................-40C to +85C MAX187_MJA/MAX189_MJA .......................-55C to +125C Storage Temperature Range............................-60C to +150C Lead Temperature (soldering, 10sec) ............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 5%; GND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187--internal reference: VREF = 4.096V, 4.7F capacitor at REF pin, or MAX189--external reference: VREF = 4.096V applied to REF pin, 4.7F capacitor at REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER DC ACCURACY (Note 1) Resolution MAX18_A Relative Accuracy (Note 2) MAX18_B MAX18_C Differential Nonlinearity Offset Error DNL No missing codes over temperature MAX18_A MAX18_B/C MAX187 Gain Error (Note 3) MAX189A MAX189B/C Gain Temperature Coefficient External reference, 4.096V 0.8 12 12 1 2 1 1
1
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
LSB
LSB LSB
2
3 3 1 3 ppm/C LSB
DYNAMIC SPECIFICATIONS (10kHz sine wave input, 0V to 4.096Vp-p, 75ksps) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Small-Signal Bandwidth Full-Power Bandwidth SINAD THD SFDR Rolloff -3dB 80 4.5 0.8 70 -80 dB dB dB MHz MHz
2
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+5V, Low-Power, 12-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%; GND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187--internal reference: VREF = 4.096V, 4.7F capacitor at REF pin, or MAX189--external reference: VREF = 4.096V applied to REF pin, 4.7F capacitor at REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate Aperture Delay Aperture Jitter ANALOG INPUT Input Voltage Range Input Capacitance (Note 4) INTERNAL REFERENCE (MAX187 only, reference buffer enabled) TA = +25C REF Output Voltage VREF TA = TMIN to TMAX REF Short-Circuit Current MAX187AC/BC REF Tempco MAX187AE/BE MAX187AM/BM MAX187C Load Regulation (Note 5) 0mA to 0.6mA output load 30 30 30 30 1 mV MAX187_C MAX187_E MAX187_M 4.076 4.060 4.050 4.040 4.096 4.116 4.132 4.140 4.150 30 50 60 80 ppm/C mA V 16 0 to VREF V pF tAPR tCONV tACQ External clock, 4MHz, 13 clocks 10 <50 5.5 1.5 75 8.5 s s ksps ns ps SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX187/MAX189
EXTERNAL REFERENCE AT REF (Buffer disabled, VREF = 4.096V) Input Voltage Range Input Current Input Resistance Shutdown REF Input Current 12 2.50 200 20 1.5 10 VDD + 50mV 350 V A k A
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3
+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%; GND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187--internal reference: VREF = 4.096V, 4.7F capacitor at REF pin, or MAX189--external reference: VREF = 4.096V applied to REF pin, 4.7F capacitor at REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, CS, SHDN) SCLK, CS Input High Voltage SCLK, CS Input Low Voltage SCLK, CS Input Hysteresis SCLK, CS Input Leakage SCLK, CS Input Capacitance SHDN Input High Voltage SHDN Input Low Voltage SHDN Input Current SHDN Input Mid Voltage SHDN Voltage, Floating SHDN Maximum Allowed Leakage, Mid Input DIGITAL OUTPUT (DOUT) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Supply Voltage VDD Operating mode Supply Current IDD Power-down mode Power-Supply Rejection PSR VDD = +5V, 5%; external reference, 4.096V; full-scale input (Note 6) MAX187 MAX189 4.75 1.5 1.0 2 0.06 5.25 2.5 2.0 10 0.5 A mV V mA VOL VOH IL COUT ISINK = 5mA ISINK = 16mA ISOURCE = 1mA CS = 5V CS = 5V (Note 4) 4 10 15 0.3 V A pF 0.4 V VINH VINL VHYST IIN CIN VINSH VINSL IINS VIM VFLT SHDN = open SHDN = open -100 SHDN = VDD or 0V 1.5 2.75 100 VIN = 0V or VDD (Note 4) VDD - 0.5 0.5 4.0 VDD -1.5 0.15 1 15 2.4 0.8 V V V A pF V V A V V nA
4
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+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
TIMING CHARACTERISTICS
(VDD = +5.0V 5%, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Track/Hold Acquisition Time SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable SCLK Clock Frequency SCLK Pulse Width High SCLK Pulse Width Low SCLK Low to CS Fall Setup Time CS Pulse Width SYMBOL tACQ tDO tDV tTR fSCLK tCH tCL tCSO tCS 100 100 50 500 CONDITIONS CS = high (Note 7) CLOAD = 100pF CLOAD = 100pF CLOAD = 100pF MAX18_ _C/E MAX18_ _M MIN 1.5 20 20 150 200 100 100 5 ns ns MHz ns ns ns ns TYP MAX UNITS s ns
Note 1: Tested at VDD = +5V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: MAX187--internal reference, offset nulled; MAX189-external +4.096V reference, offset nulled. Excludes reference errors. Note 4: Guaranteed by design. Not subject to production testing. Note 5: External load should not change during conversion for specified ADC accuracy. Note 6: DC test, measured at 4.75V and 5.25V only. Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired.
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5
+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
________________________________________________Typical Operating Characteristics
POWER-SUPPLY REJECTION vs. TEMPERATURE
0.16 INTERNAL REFERENCE VOLTAGE (V) POWER-SUPPLY REJECTION (mV) 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 -60 -20 20 60 100 140 4.090 4.089 4.088 4.087 4.086 4.085 4.084 4.083 4.082 4.081 4.080 -60 -20 20 60 100 140
VREF vs. TEMPERATURE
TEMPERATURE (C)
TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE
7 SHUTDOWN SUPPLY CURRENT (A) 2.2 SUPPLY CURRENT (mA) 1.8 MAX187 1.4 1.0 0.6 0.2 0 -60 -20 20 60 100 140 -60 MAX189 6 5 4 3 2 1
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
-20
20
60
100
140
TEMPERATURE (C)
TEMPERATURE (C)
6
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+5V, Low-Power, 12-Bit Serial ADCs
_______________________________________________________________________Pin Description
PIN DIP 1 2 WIDE SO 1 3 NAME VDD AIN Supply voltage, +5V 5% Sampling analog input, 0V to VREF range Three-level shutdown input. Pulling SHDN low shuts the MAX187/MAX189 down to 10A (max) supply current. Both MAX187 and MAX189 are fully operational with either SHDN high or floating. For the MAX187, pulling SHDN high enables the internal reference, and letting SHDN float disables the internal reference and allows for the use of an external reference. Reference voltage--sets analog voltage range and functions as a 4.096V output for the MAX187 with enabled internal reference. REF also serves as a +2.5V to VDD input for a precision reference for both MAX187 (disabled internal reference) and MAX189. Bypass with 4.7F if internal reference is used, and with 0.1F if an external reference is applied. Analog and digital ground Analog ground Digital ground Serial data output. Data changes state at SCLK's falling edge. Active-low chip select initiates conversions on the falling edge. When CS is high, DOUT is high impedance. Serial clock input. Clocks data out with rates up to 5MHz. Not internally connected. Connect to AGND for best noise performance. FUNCTION
MAX187/MAX189
3
6
SHDN
4
8
REF
5 -- -- 6 7 8 --
-- 10 11 12 15 16 2,4,5,7,9,13,14
GND AGND DGND DOUT CS SCLK N.C.
_______________Detailed Description
Converter Operation
The MAX187/MAX189 use input track/hold (T/H) and successive approximation register (SAR) circuitry to convert an analog input signal to a digital 12-bit output. No external hold capacitor is needed for the T/H. Figures 3a and 3b show the MAX187/MAX189 in their simplest configuration. The MAX187/MAX189 convert input signals in the 0V to VREF range in 10s, including T/H acquisition time. The MAX187's internal reference is trimmed to 4.096V, while the MAX189 requires an external reference. Both devices accept external reference voltages from +2.5V to VDD. The serial interface requires only three digital lines, SCLK, CS, and DOUT, and provides easy interface to microprocessors (Ps). Both converters have two modes: normal and shutdown. Pulling SHDN low shuts the device down and reduces supply current to below 10A, while pulling SHDN high or leaving it floating puts the device into the operational mode. A conversion is initiated by CS falling. The conversion result is available at DOUT in
unipolar serial format. A high bit, signaling the end of conversion (EOC), followed by the data bits (MSB first), make up the serial data stream. The MAX187 operates in one of two states: (1) internal reference and (2) external reference. Select internal reference operation by forcing SHDN high, and external reference operation by floating SHDN.
Analog Input
Figure 4 illustrates the sampling architecture of the ADC's analog comparator. The full-scale input voltage depends on the voltage at REF. REFERENCE Internal Reference (MAX187 only) External Reference ZERO SCALE 0V 0V FULL SCALE +4.096V VREF
For specified accuracy, the external reference voltage range spans from +2.5V to VDD.
_______________________________________________________________________________________
7
+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
+5V
3k DOUT DOUT
3k
CLOAD = 100pF
CLOAD = 100pF
DGND a. High-Z to VOH and VOL to VOH
DGND b. High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for DOUT Enable Time
+5V
3k DOUT DOUT
3k
CLOAD = 100pF
CLOAD = 100pF
DGND a. VOH to High-Z
DGND b. VOLto High-Z
Figure 2. Load Circuits for DOUT Disable Time
8
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+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
4.7F 0.1F 4.7F 0.1F
+5V ANALOG INPUT 0V TO +5V SHUTDOWN INPUT OFF 4.7F
1 2 3
VDD
SCLK
8 7 6 5 SERIAL INTERFACE
+5V ANALOG INPUT 0V TO +5V SHUTDOWN INPUT OFF REFERENCE INPUT
1 2 3
VDD
SCLK
8 7 6 5 SERIAL INTERFACE
AIN MAX187 CS SHDN REF DOUT GND
AIN MAX189 CS SHDN REF DOUT GND
ON 4
ON 4
0.1F
Figure 3a. MAX187 Operational Diagram
Figure 3b. MAX189 Operational Diagram
12-BIT CAPACITIVE DAC REF AIN TRACK INPUT CHOLD -+ 16pF CSWITCH TRACK 5k RIN HOLD AT THE SAMPLING INSTANT, THE INPUT SWITCHES FROM AIN TO GND. COMPARATOR ZERO
HOLD CPACKAGE
GND
Figure 4. Equivalent Input Circuit
Track/Hold In track mode, the analog signal is acquired and stored in the internal hold capacitor. In hold mode, the T/H switch opens and maintains a constant input to the ADC's SAR section. During acquisition, the analog input AIN charges capacitor CHOLD. Bringing CS low ends the acquisition
interval. At this instant, the T/H switches the input side of CHOLD to GND. The retained charge on CHOLD represents a sample of the input, unbalancing the node ZERO at the comparator's input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of a 12-bit resolution. This action is equivalent to transferring a charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. At the conversion's end, the input side of CHOLD switches back to AIN, and CHOLD charges to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. Acquisition time is calculated by: tACQ = 9 (RS + RIN) 16pF, where RIN = 5k, RS = the source impedance of the input signal, and tACQ is never less than 1.5s. Source impedances below 5k do not significantly affect the AC performance of the ADC.
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9
+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
Input Bandwidth The ADCs' input tracking circuitry has a 4.5MHz smallsignal bandwidth, and an 8V/s slew rate. It is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of interest, an anti-alias filter is recommended. See the MAX274/MAX275 continuous-time filters data sheet. Input Protection Internal protection diodes that clamp the analog input allow the input to swing from GND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale, the input must not exceed VDD by more than 50mV, or be lower than GND by 50mV. If the analog input exceeds the supplies by more than 50mV beyond the supplies, limit the input current to 2mA, since larger currents degrade conversion accuracy. Driving the Analog Input The input lines to AIN and GND should be kept as short as possible to minimize noise pickup. Shield longer leads. Also see the Input Protection section. Because the MAX187/MAX189 incorporate a T/H, the drive requirements of the op amp driving AIN are less stringent than those for a successive-approximation ADC without a T/H. The typical input capacitance is 16pF. The amplifier bandwidth should be sufficient to handle the frequency of the input signal. The MAX400 and OP07 work well at lower frequencies. For higherfrequency operation, the MAX427 and OP27 are practical choices. The allowed input frequency range is limited by the 75ksps sample rate of the MAX187/MAX189. Therefore, the maximum sinusoidal input frequency allowed is 37.5kHz. Higher-frequency signals cause aliasing problems unless undersampling techniques are used.
Reference
The MAX187 can be used with an internal or external reference, while the MAX189 requires an external reference.
Internal Reference The MAX187 has an on-chip reference with a buffered temperature-compensated bandgap diode, lasertrimmed to +4.096V 0.5%. Its output is connected to REF and also drives the internal DAC. The output can be used as a reference voltage source for other components and can source up to 0.6mA. Decouple REF with a 4.7F capacitor. The internal reference is enabled by pulling the SHDN pin high. Letting SHDN float disables the internal reference, which allows the use of an external reference, as described in the External Reference section. External Reference The MAX189 operates with an external reference at the REF pin. To use the MAX187 with an external reference, disable the internal reference by letting SHDN float. Stay within the voltage range +2.5V to VDD to achieve specified accuracy. The minimum input impedance is 12k for DC currents. During conversion, the external reference must be able to deliver up to 350A DC load current and have an output impedance of 10 or less. The recommended minimum value for the bypass capacitor is 0.1F. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7F capacitor.
COMPLETE CONVERSION SEQUENCE CS tWAKE SHDN
DOUT CONVERSION 0 POWERED UP POWERED DOWN CONVERSION 1 POWERED UP
Figure 5. MAX187/MAX189 Shutdown Sequence
10
______________________________________________________________________________________
+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
10000 3.0 2.5 1000 SUPPLY CURRENT (A) MAX187 100 tWAKE (ms) MAX189* 10 0.5 1 0.1 1 10 *REF CONNECTED TO VDD 100 1000 10000 100000 0 0.0001 0.001 0.01 0.1 1 10 CONVERSIONS PER SECOND 2.0 1.5 1.0
TIME IN SHUTDOWN (sec)
Figure 6. Average Supply Current vs. Conversion Rate
Figure 7. tWAKE vs. Time in Shutdown (MAX187 only)
____________________Serial Interface
Initialization After Power-Up and Starting a Conversion
When power is first applied, it takes the fully discharged 4.7F reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. With SHDN not pulled low, the MAX187/MAX189 are now ready to convert. To start a conversion, pull CS low. At CS's falling edge, the T/H enters its hold mode and a conversion is initiated. After an internally timed 8.5s conversion period, the end of conversion is signaled by DOUT pulling high. Data can then be shifted out serially with the external clock.
External Clock
The actual conversion does not require the external clock. This frees the P from the burden of running the SAR conversion clock, and allows the conversion result to be read back at the P's convenience at any clock rate from 0MHz to 5MHz. The clock duty cycle is unrestricted if each clock phase is at least 100ns. Do not run the clock while a conversion is in progress.
Timing and Control
Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs. The timing diagrams of Figures 8 and 9 outline the operation of the serial interface. A CS falling edge initiates a conversion sequence: The T/H stage holds input voltage, the ADC begins to convert, and DOUT changes from high impedance to logic low. SCLK must be kept inactive during the conversion. An internal register stores the data when the conversion is in progress. End of conversion (EOC) is signaled by DOUT going high. DOUT's rising edge can be used as a framing signal. SCLK shifts the data out of this register any time after the conversion is complete. DOUT transitions on SCLK's falling edge. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are 12 data bits and one leading high bit, at least 13 falling clock edges are needed to shift out these bits. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CS, produce trailing 0s at DOUT and have no effect on converter operation.
11
Using
Power consumption can be reduced significantly by shutting down the MAX187/MAX189 between conversions. This is shown in Figure 6, a plot of average supply current vs. conversion rate. Because the MAX189 uses an external reference voltage (assumed to be present continuously), it "wakes up" from shutdown more quickly, and therefore provides lower average supply currents. The wakeup-time, tWAKE, is the time from SHDN deasserted to the time when a conversion may be initiated. For the MAX187, this time is 2s. For the MAX189, this time depends on the time in shutdown (see Figure 7) because the external 4.7F reference bypass capacitor loses charge slowly during shutdown (see the specifications for shutdown, REF Input Current = 10A max).
SHDN to Reduce Supply Current
______________________________________________________________________________________
+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
CS 1 SCLK DOUT CONVERSION IN PROGRESS CONVERSION 0 EOC EOC B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 TRAILING ZEROS 4 8 12
INTERFACE IDLE A/D STATE TRACK
CLOCK OUTPUT DATA TRACK
IDLE CONV. 1
MINIMUM CYCLE TIME
8.5s (tCONV)
0s
12 x 0.250s = 3.25s TOTAL = 12.25s
0s
0.5s (tCS)
Figure 8. MAX187/MAX189 Interface Timing Sequence
CS
tCS
...
tCS0 tCH
...
SCLK tCONV tDO tDV DOUT tAPR tCL tTR B1 B0
...
B2
INTERNAL T/H
(TRACK)
(HOLD)
...
(TRACK)
Figure 9. MAX187/MAX189 Detailed Serial-Interface Timing
12
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+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
20 OUTPUT CODE 11...111 11...110 11...101 AMPLITUDE (dB) -40 FULL-SCALE TRANSITION 0
fS = 75ksps fT = 10kHz TA = +25C
-20
FS = +4.096V 1LSB = FS 4096 00...011 00...010 00...001 00...000 0 1 2 3 FS - 3/2LSB FS INPUT VOLTAGE (LSBs)
-60
-80
-100
-120 -140 0 18.75 FREQUENCY (kHz) 37.5
Figure 10. MAX187/MAX189 Unipolar Transfer Function, 4.096V = Full Scale
Figure 11. MAX187/MAX189 FFT plot
Minimum cycle time is accomplished by using DOUT's rising edge as the EOC signal. Clock out the data with 13 clock cycles at full speed. Raise CS after the conversion's LSB has been read. After the specified minimum time, tACQ, CS can be pulled low again to initiate the next conversion.
Output Coding and Transfer Function
The data output from the MAX187/MAX189 is binary, and Figure 10 depicts the nominal transfer function. Code transitions occur halfway between successive integer LSB values. If V REF = +4.096V, then 1 LSB = 1.00mV or 4.096V/4096.
input frequency. ADCs have traditionally been evaluated by specifications such as Zero and Full-Scale Error, Integral Nonlinearity (INL), and Differential Nonlinearity (DNL). Such parameters are widely accepted for specifying performance with DC and slowly varying signals, but are less useful in signal-processing applications, where the ADC's impact on the system transfer function is the main concern. The significance of various DC errors does not translate well to the dynamic case, so different tests are required.
Signal-to-Noise Ratio and Effective Number of Bits
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS amplitude of all other ADC output signals. The input bandwidth is limited to frequencies above DC and below one-half the ADC sample (conversion) rate. The theoretical minimum ADC noise is caused by quantization error and is a direct result of the ADC's resolution: SINAD = (6.02N + 1.76)dB, where N is the number of bits of resolution. An ideal 12-bit ADC can, therefore, do no better than 74dB. An FFT plot of the output shows the output level in various spectral bands. Figure 11 shows the result of sampling a pure 10kHz sine wave at a 75ksps rate with the MAX187/MAX189.
13
_____________Dynamic Performance
High-speed sampling capability and a 75ksps throughput make the MAX187/MAX189 ideal for wideband signal processing. To support these and other related applications, Fast Fourier Transform (FFT) test techniques are used to guarantee the ADC's dynamic frequency response, distortion, and noise at the rated throughput. Specifically, this involves applying a lowdistortion sine wave to the ADC input and recording the digital conversion results for a specified time. The data is then analyzed using an FFT algorithm that determines its spectral content. Conversion errors are then seen as spectral elements outside of the fundamental
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+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
12.2 12.0 11.8 11.6 11.4 EFFECTIVE BITS 11.2 11.0 10.8 10.6 10.4 10.2 1 10 (UNDERSAMPLED) a. SPI 100 1000 CS SCK MISO +5V CS SCLK DOUT SS I/O SCK MISO +5V CS SCLK DOUT
MAX187 MAX189
INPUT FREQUENCY (kHz)
Figure 12. Effective Bits vs. Input Frequency
The effective resolution (effective number of bits) the ADC provides can be determined by transposing the above equation and substituting in the measured SINAD: N = (SINAD - 1.76)/6.02. Figure 12 shows the effective number of bits as a function of the input frequency for the MAX187/MAX189.
MAX187 MAX189
SS
b. QSPI
Total Harmonic Distortion
If a pure sine wave is sampled by an ADC at greater than the Nyquist frequency, the nonlinearities in the ADC's transfer function create harmonics of the input frequency present in the sampled output data. Total Harmonic Distortion (THD) is the ratio of the RMS sum of all the harmonics (in the frequency band above DC and below one-half the sample rate, but not including the DC component) to the RMS amplitude of the fundamental frequency. This is expressed as follows: THD = 20log
I/O SK SI
CS SCLK DOUT
MAX187 MAX189
V22 + V32 + V42 + ... VN2
V1
c. MICROWIRE
where V1 is the fundamental RMS amplitude, and V2 through VN are the amplitudes of the 2nd through Nth harmonics. The THD specification in the Electrical Characteristics includes the 2nd through 5th harmonics.
Figure 13. Common Serial-Interface Connections to the MAX187/MAX189
14
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+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
____________Applications Information
Connection to Standard Interfaces
The MAX187/MAX189 serial interface is fully compatible with SPI, QSPI, and Microwire standard serial interfaces. If a serial interface is available, set the CPU's serial interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 2.5MHz. 1. Use a general-purpose I/O line on the CPU to pull CS low. Keep SCLK low. 2. Wait the for the maximum conversion time specified before activating SCLK. Alternatively, look for a DOUT rising edge to determine the end of conversion. 3. Activate SCLK for a minimum of 13 clock cycles. The first falling clock edge will produce the MSB of the DOUT conversion. DOUT output data transitions on SCLK's falling edge and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Data can be clocked into the P on SCLK's rising edge. 4. Pull CS high at or after the 13th falling clock edge. If CS remains low, trailing zeros are clocked out after the LSB. 5. With CS = high, wait the minimum specified time, tCS, before launching a new conversion by pulling CS low. If a conversion is aborted by pulling CS high before the conversions end, wait for the minimum acquisition time, t ACQ , before starting a new conversion. Data can be output in 1-byte chunks or continuously, as shown in Figure 8. The bytes will contain the result of the conversion padded with one leading 1, and trailing 0s if SCLK is still active with CS kept low.
1ST BYTE READ SCLK CS HI-Z DOUT tCONV MSB D10 D9 D8 D7 D6 D5 D4 D3 D2
2ND BYTE READ
HI-Z D1 LSB
EOC
Figure 14. SPI/Microwire Serial Interface Timing (CPOL = CPHA = 0)
SCLK CS HI-Z DOUT tCONV MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB HI-Z
EOC
Figure 15. QSPI Serial Interface Timing (CPOL = CPHA = 0)
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15
+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
SPI and Microwire
When using SPI or QSPI, set CPOL = 0 and CPHA = 0. Conversion begins with a CS falling edge. DOUT goes low, indicating a conversion in progress. Wait until DOUT goes high or the maximum specified 8.5s conversion time. Two consecutive 1-byte reads are required to get the full 12 bits from the ADC. DOUT output data transitions on SCLK's falling edge and is clocked into the P on SCLK's rising edge. The first byte contains a leading 1 and 7 bits of conversion result. The second byte contains the remaining 5 bits and 3 trailing 0s. See Figure 13 for connections and Figure 14 for timing. 12 bits of data with no trailing 0s (Figure 15). The maximum clock frequency to ensure compatibility with QSPI is 2.77MHz.
Opto-Isolated Interface, Serial-to-Parallel Conversion
Many industrial applications require electrical isolation to separate the control electronics from hazardous electrical conditions, provide noise immunity, or prevent excessive current flow where ground disparities exist between the ADC and the rest of the system. Isolation amplifiers typically used to accomplish these tasks are expensive. In cases where the signal is eventually converted to a digital form, it is cost effective to isolate the input using opto-couplers in a serial link. The MAX187 is ideal in this application because it includes both T/H amplifier and voltage reference, operates from a single supply, and consumes very little power (Figure 16).
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two 1-byte reads to acquire the 12 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX187/MAX189 require 13 clock cycles from the P to clock out the
+5V ON THIS SIDE OF BARRIER MUST BE ISOLATED POWER +5V 8 3k 7 6 10F 5
CS/START
6N136
1 2 3 4
+5V 200 14
SCLK/INPUT CLOCK QH QG 74HC595 QF 11 QE SCK QD 12 QC RCK QB 10 QA SCLR SER 13 9 QH 8 0.1F 7 6 5 4 3 2 1 15 16
MAX187
0.1F 1 2 4 ANALOG INPUT 4.7F 5 VDD AIN REF GND SHDN CS SCLK DOUT 3 7 8 6 470 3k 8 7 6 5
6N136
1 2 3 4 200
74HC04
74HC04
D11 (MSB) D10 D9 D8 +5V
6N136
1 2 SIGNAL GROUND 3 4 8 7 6 5 8.2k
QH QG 74HC595 QF 11 QE SCK QD 12 QC RCK QB 10 QA +5V SCLR 14 SER 13 8
7 6 5 4 3 2 1 15 16
D7 D6 D5 D4 D3 D2 D1 D0(LSB) +5V 0.1F
Figure 16. 12-Bit Isolated ADC
16
______________________________________________________________________________________
+5V, Low-Power, 12-Bit Serial ADCs
The ADC results are transmitted across a 1500V isolation barrier provided by three 6N136 opto-isolators. Isolated power must be supplied to the converter and the isolated side of the opto-couplers. 74HC595 threestate shift registers are used to construct a 12-bit parallel data output. The timing sequence is identical to the timing shown in Figure 8. Conversion speed is limited by the delay through the opto-isolators. With a 140kHz clock, conversion time is 100s. The universal 12-bit parallel data output can also be used without the isolation stage when a parallel interface is required. Clock frequencies up to 2.9MHz are possible without violating the 20ns shift-register setup time. Delay or invert the clock signal to the shift registers beyond 2.9MHz.
MAX187/MAX189
SUPPLIES +5V GND
R* = 10 4.7F
0.01F VDD AGND DGND +5V DGND
Layout, Grounding, Bypassing
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 17 shows the recommended system ground connections. A single-point analog ground ("star" ground point) should be established at GND, separate from the logic ground. All other analog grounds should be connected to this ground. The 16-pin versions also have a dedicated DGND pin available. Connect DGND to this star ground point for further noise reduction. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the V DD power supply may affect the ADC's high-speed comparator. Bypass this supply to the single-point analog ground with 0.01F and 4.7F bypass capacitors. Minimize capacitor lead lengths for best supply-noise rejection. If the +5V power supply is very noisy, a 10 resistor can be connected as a lowpass filter to attenuate supply noise (Figure 17).
MAX187 MAX189
*OPTIONAL
DIGITAL CIRCUITRY
Figure 17. Power-Supply Grounding Condition
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17
+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
__Ordering Information (continued)
PART MAX187AEPA MAX187BEPA MAX187CEPA MAX187AEWE MAX187BEWE MAX187AMJA MAX187BMJA MAX189ACPA MAX189BCPA MAX189CCPA MAX189ACWE MAX189BCWE MAX189CCWE MAX189BC/D MAX189AEPA MAX189BEPA MAX189CEPA MAX189AEWE MAX189BEWE MAX189AMJA MAX189BMJA TEMP. RANGE PIN-PACKAGE ERROR (LSB) -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 8 Plastic DIP 8 Plastic DIP 8 Plastic DIP 16 Wide SO 16 Wide SO 16 Wide SO 8 CERDIP** 8 CERDIP** 8 Plastic DIP 8 Plastic DIP 8 Plastic DIP 16 Wide SO 16 Wide SO 16 Wide SO Dice* 8 Plastic DIP 8 Plastic DIP 8 Plastic DIP 16 Wide SO 16 Wide SO 16 Wide SO 8 CERDIP** 8 CERDIP** 12 1 2 12 1 2 12 1 12 1 2 12 1 2 1 12 1 2 12 1 2 12 1
V DD 1 N.C. 2 AIN 3 N.C. 4 N.C. 5 SHDN 6 N.C. 7 REF 8 16 SCLK 15 CS 14 N.C.
____Pin Configurations (continued)
MAX187CEWE -40C to +85C
MAX187 MAX189
13 N.C. 12 DOUT 11 DGND 10 AGND 9 N.C.
Wide SO
MAX189CEWE -40C to +85C
* Dice are specified at TA = +25C, DC parameters only. **Contact factory for availability and processing to MIL-STD-883.
18
______________________________________________________________________________________
+5V, Low-Power, 12-Bit Serial ADCs
___________________Chip Topography
MAX187/MAX189
V DD SCLK CS AIN
MAX187/MAX189
0.151" (3.84mm)
DOUT
SHDN REF 0.117" (2.97mm) AGND AGND
DGND
TRANSISTOR COUNT: 2278; SUBSTRATE CONNECTED TO VDD.
______________________________________________________________________________________
19
+5V, Low-Power, 12-Bit Serial ADCs MAX187/MAX189
________________________________________________________________Package Information
DIM
E A2 A D A3 E1
A A1 A2 A3 B B1 C D1 E E1 e eA eB L
0-15 A1 L B D1 e B1 eA eB C
P PACKAGE PLASTIC DUAL-IN-LINE
INCHES MAX MIN 0.200 - - 0.015 0.175 0.125 0.080 0.055 0.020 0.016 0.065 0.045 0.012 0.008 0.090 0.050 0.625 0.600 0.575 0.525 - 0.100 - 0.600 0.700 - 0.150 0.120 INCHES MIN MAX 1.230 1.270 1.430 1.470 2.025 2.075
MILLIMETERS MIN MAX - 5.08 0.38 - 3.18 4.45 1.40 2.03 0.41 0.51 1.14 1.65 0.20 0.30 1.27 2.29 15.24 15.88 13.34 14.61 2.54 - 15.24 - - 17.78 3.05 3.81 MILLIMETERS MIN MAX 31.24 32.26 36.32 37.34 51.44 52.71
DIM PINS D D D 24 28 40
DIM
D 0- 8 A e B
0.101mm 0.005in.
A1
C
L
A A1 B C E e H L
INCHES MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.299 0.291 0.050 0.419 0.394 0.050 0.016
MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.35 0.49 0.23 0.32 7.40 7.60 1.27 10.00 10.65 0.40 1.27
DIM PINS
E
H
W PACKAGE SMALL OUTLINE
D D D D D
16 18 20 24 28
INCHES MIN MAX 0.398 0.413 0.447 0.463 0.496 0.512 0.598 0.614 0.697 0.713
MILLIMETERS MIN MAX 10.10 10.50 11.35 11.75 12.60 13.00 15.20 15.60 17.70 18.10
21-0042A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1993 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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